When scaling for next generation semiconductor devices in connection with increased miniaturization, including, for example, very-large-scale integration (VLSI), back end of line (BEOL) resistance can be a critical issue affecting device performance. In interconnect metallurgy, the formation of metallization with a microstructure that minimizes grain boundaries that lie parallel to current flow mitigates the effects of electromigration-induced voiding.
As scaling of device dimensions in microelectronic circuitry has dictated a need for smaller interconnect trench widths, the corresponding aspect ratios of these trenches have increased in order to maximize a cross-section of the interconnect. Conventional fabrication of such trenches, which uses copper electroplating, can produce small grains whose grain boundaries are more susceptible to electromigration effects.
As the copper (Cu) interconnect dimensions become smaller, resistivity of the interconnect increases dramatically. This becomes a challenge for the development of current and future semiconductor technology nodes. It has been observed that copper interconnect structures possessing columnar metallic thin films are superior to those with a polycrystalline structure with respect to mechanical and electrical properties, providing increased mechanical strength and electrical conductivity (i.e., lower resistivity).